// Version 1 of module for comparison test
module test_module (
    input wire clk,
    input wire rst_n,
    input wire [7:0] data_in,
    output wire [7:0] data_out,
    output wire valid
);

parameter WIDTH = 8;
parameter DEPTH = 16;

reg [7:0] internal_reg;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        internal_reg <= 8'h0;
    else
        internal_reg <= data_in;
end

assign data_out = internal_reg;
assign valid = 1'b1;

endmodule
